VHDL - Testbench
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-- Company:
-- Engineer:
--
-- Create Date: 01:42:19 01/15/2015
-- Design Name:
-- Module Name: D:/Xilinx_Workspace/code8/tb_code8.vhd
-- Project Name: code8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: code8
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_code8 IS
END tb_code8;
ARCHITECTURE behavior OF tb_code8 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT code8
PORT(
clk : IN bit;
A : IN bit;
B : IN bit;
Y : OUT bit
);
END COMPONENT;
--Inputs
signal clk : bit;
signal A : bit;
signal B : bit;
--Outputs
signal Y : bit;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
A <= '0', '1' after 20ns, '0' after 40ns;
B <= '0', '1' after 10ns, '0' after 20ns, '1' after 30ns, '0' after 40ns;
-- Instantiate the Unit Under Test (UUT)
uut: code8 PORT MAP (
clk => clk,
A => A,
B => B,
Y => Y
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;